Solana
System Architecture
Context
This figure appears in the 'System Architecture' section, which describes how Solana's Transaction Processing Unit (TPU) is organized as a multi-stage hardware pipeline. The section explains that each pipeline stage operates concurrently on different batches of transactions — analogous to a CPU instruction pipeline — ensuring that no single stage becomes the bottleneck and that all available hardware (network interface, GPU, CPU cores, storage) is continuously utilized.
What This Figure Shows
The diagram depicts the four-stage TPU pipeline: the Fetch stage receives UDP transaction packets from the network and performs basic structural validation; the SigVerify stage offloads Ed25519 signature verification to GPU using CUDA, processing nearly one million signatures per second in parallel; the Banking stage executes transactions against the current ledger state using the Sealevel parallel smart contract runtime, which schedules non-conflicting transactions across multiple CPU cores based on declared account access sets; and the Write stage commits executed transactions to the ledger, incorporates them into the PoH sequence, and transmits the resulting block via the Turbine protocol. While the Banking stage processes one batch, the SigVerify stage is already validating the next batch, and the Fetch stage is receiving the batch after that — maximizing hardware utilization.
Significance
The pipelined architecture is Solana's primary mechanism for achieving high transaction throughput without sacrificing verification quality. By separating signature verification (GPU-bound), execution (CPU-bound, parallelizable across accounts), and I/O (network and storage) into concurrent stages, Solana avoids the sequential bottleneck present in single-threaded blockchain runtimes. This diagram is the clearest illustration of why Solana can target 50,000+ transactions per second at the protocol level.
